Freescale Semiconductor /MKL28T7_CORE1 /SCG /SOSCDIV

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SOSCDIV

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (000)SOSCDIV1 0 (000)SOSCDIV2 0 (000)SOSCDIV3

SOSCDIV3=000, SOSCDIV2=000, SOSCDIV1=000

Description

System OSC Divide Register

Fields

SOSCDIV1

System OSC Clock Divide 1

0 (000): Output disabled

1 (001): Divide by 1

2 (010): Divide by 2

3 (011): Divide by 4

4 (100): Divide by 8

5 (101): Divide by 16

6 (110): Divide by 32

7 (111): Divide by 64

SOSCDIV2

System OSC Clock Divide 2

0 (000): Output disabled

1 (001): Divide by 1

2 (010): Divide by 2

3 (011): Divide by 4

4 (100): Divide by 8

5 (101): Divide by 16

6 (110): Divide by 32

7 (111): Divide by 64

SOSCDIV3

System OSC Clock Divide 3

0 (000): Output disabled

1 (001): Divide by 1

2 (010): Divide by 2

3 (011): Divide by 4

4 (100): Divide by 8

5 (101): Divide by 16

6 (110): Divide by 32

7 (111): Divide by 64

Links

() ()